IMPLEMENTATION OF NON- HIERARCHICAL8X2ADDERCOMPRESSOR

Abstract

The available Adder Compressor do not handle efficiently. The non-hierarchical 8X2adder compressor is a high-speed combinational circuit designed to reduce eight input bits into two output sum bits and a carry-out. This circuit is integral to arithmetic units in applications such as multipliers and digital signal processing, where efficient bit compression is crucial for performance. The design leverages the high-speed and low-power characteristics of 32nm CMOS technology to achieve minimal propagation delay and optimized area utilization. It employs a flat, non-hierarchical structure using XOR, AND, and OR gates to compute partial sums and carry bits efficiently, ensuring reduced logic depth and critical path delays. The three-stage process includes grouping inputs, generating intermediate results, and producing final outputs, enabling high-through put operation suitable for modern VLSI systems. Key features of the non-hierarchical 8X2 adder compressor include its simplicity, reduced logic levels, and adaptability for high-speed arithmetic processing. This circuit is particularlywellsuitedformoderndigitalsystemsrequiringcompactandefficientcombinationallogicsolutions. The results have been designed and verified with HSPICE using CMOS 32-nm technology.